@HarneyBA node sizes are determined such that each node size decrease translates to a doubling of transistor density.
Ie for planar transistors, the drop from 45nm to 32nm doubled the number of transistors per square millimeter.
Of course, the cost of each node drop is greater than the gain in transistor density
@HarneyBA that doesn't hold up anymore, however, in the era of FinFET transistors. Intel has been FinFET since 22nm, and pretty much every node smaller than that in the industry is also FinFET.
Node size in FinFET era is also mostly meaningless below 15nm, because it doesn't account for fin pitch and density in any way
@HarneyBA cost goes up a huge amount from this point forward. Below 10nm it requires new UV technology that is only just now coming to fruition.
450mm wafers are also just around the corner, and when they are ready, the ENTIRE industry will move to them at the same time. That will require ENORMOUS capital expense the likes we haven't seen since 300mm wafers came out
Also for 3D chips my understanding is that they separate the "layers" with a glass like substance? If they were to only create two layers and pull heat from either side would that solve the thermal issue while still allowing for shorter connections? Obviously I'm no where near qualified to even ask the question properly so pardon my ignorance.
@AtypicalKernel @HarneyBA Applying that to 3d chips, once you start dealing with a chip that is an order of magnitude thicker than before, the very center of the chip will be very hard to keep thermally regulated.
The very same properties in materials you want for electrical insulation also, unfortunately, translate into heat insulation. They are intrinsically the same property, and I'm not aware of many materials that are great heat conductors and poor electrical conductors at the same time.
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