@villain if you are concerned about government backdoors in hardware, then you will need to fully audit the hardware from design specs all the way through fabrication. As long as you rely on others to build something on your behalf, and not do it yourself, you are at risk.
The downside of this is that you are going to need over 20 gigadollars to build a state-of-the-art factory and pay for the personnel for several years.
@matt Thats really cool! That's a pretty big interest of mine! (bellow programming, but still, pretty high up on my interests).
@OpenComputeDesign I still have an interest in programming, but I often have a hard time wrapping my head around some programming concepts. Programing is more art than science, and I am a terrible artist.
@matt I don't know, silicon chips are really pretty! lol. Seriously though, semiconductor processing is really cool, much respect.
@OpenComputeDesign Little known fact:
The sound of a wafer breaking is one of the most expensive sounds in the world.
@HarneyBA node sizes are determined such that each node size decrease translates to a doubling of transistor density.
Ie for planar transistors, the drop from 45nm to 32nm doubled the number of transistors per square millimeter.
Of course, the cost of each node drop is greater than the gain in transistor density
@HarneyBA that doesn't hold up anymore, however, in the era of FinFET transistors. Intel has been FinFET since 22nm, and pretty much every node smaller than that in the industry is also FinFET.
Node size in FinFET era is also mostly meaningless below 15nm, because it doesn't account for fin pitch and density in any way
@HarneyBA cost goes up a huge amount from this point forward. Below 10nm it requires new UV technology that is only just now coming to fruition.
450mm wafers are also just around the corner, and when they are ready, the ENTIRE industry will move to them at the same time. That will require ENORMOUS capital expense the likes we haven't seen since 300mm wafers came out
@HarneyBA why move to 450mm you ask? 450mm will result in a 2.25x greater die per wafer, while maintaining CURRENT cost/wafer.
We saw the same benefits with each wafer size jump, from 100mm -> 150mm -> 200mm -> 300mm.
Of course. That ignores cost of new equipment and R&D.
@HarneyBA A modern photolithography machine capable of laying patterns for 14nm nodes can easily cost $100M EACH. Most other tools cost around $5M-10M each, too.
@HarneyBA Of course.
Its fun to see hobbyists try to make usable devices with non-industry tools, but it cannot scale without gigantic capital investment if you are starting from scratch. Even if you want to borrow a foundry fab, you will still need gigantic financial investment *just* for the photomasks.
Also for 3D chips my understanding is that they separate the "layers" with a glass like substance? If they were to only create two layers and pull heat from either side would that solve the thermal issue while still allowing for shorter connections? Obviously I'm no where near qualified to even ask the question properly so pardon my ignorance.
There is actually no more interest in the industry to do it, despite the obvious benefits. Equipment manufacturers don't want to end-of-life their current 300mm tech, fabs don't want to have to completely retool, and we would have to learn the painful lessons of going up a wafer size again.
Going from 200mm to 300mm wafers was a VERY painful experience for the industry, even moreso than going from any other size up to 200mm.
Here's the thing about chips and heat dissipation. Think of it like cooking a turkey. The outside of the turkey is VERY easy to cook and cook rapidly, but the core of the turkey takes hours. This is because of the thermal properties of turkey meat.
When cooling something, the opposite is also true. Those very same properties that make heating a turkey slow, also make cooling the inside of a turkey slow.
@AtypicalKernel @HarneyBA Applying that to 3d chips, once you start dealing with a chip that is an order of magnitude thicker than before, the very center of the chip will be very hard to keep thermally regulated.
The very same properties in materials you want for electrical insulation also, unfortunately, translate into heat insulation. They are intrinsically the same property, and I'm not aware of many materials that are great heat conductors and poor electrical conductors at the same time.
@Shufei Its very unlikely unless someone discovers a new process. You *need* very strong chemicals to break up oxide bonds; you literally cannot break up silicon oxides without a fluorine-based process (liquid HF or F+ ions in a plasma)
@tradjincal I cannot answer that in an official capacity, other than to give the generic statement that Intel is always conducting R&D into the best manufacturing process.
@matt Do you have any thoughts/opinions on in-house fabrication (Intel) vs 3rd party (AMD/TSMC) and the benefits or drawbacks for each?
@Maldron I strongly believe it was a mistake for AMD to spin off GlobalFoundries into its own company. You decouple the chip design team from the fab R&D team, and it is much harder to get them to work together. Additionally you are outsourcing your Q&A, and open yourself up to IP theft. (Continued)
@Maldron Apple ditching Intel for their own ARM chips in their Mac line? Give them a couple years and they will open their own R&D fab, and by decades end they will drop TSMC and Foxconn as suppliers.
@Maldron on the other hand, for smaller players it makes sense to go "fabless". Running your own fab with state of the art tech is not cheap (Fab42 for example cost Intel at least $5B to build and at least $5B more to put the equipment in, not to mention the ongoing cost).
@Maldron if you don't own your own fab, you have less control over your own destiny.
Imagine how AMD will feel when they can't get their next Ryzen line out the door because Apple decided to buy up all of TSMC's and GlobalFoundries' capacity first.
Linux geeks doing what Linux geeks do...